The ADC provides a rich portfolio with a resolution from 10 to 12-bit, maximum speed up to 5MSPS, and supports input types of single-ended or differential that give users great flexibility in their ASIC/SoC integration.
Thanks to the patented innovative circuit techniques, the ADC can perform conversion as fast as the clock rate that is not commonly seen in the conventional ADCs which often require a clock rate (Bit+N) X faster than the conversion rate. This feature eases the design complexity of system clock arrangement (and also the PLL/OSC) and saves power because of a reduced clock rate used by the ADC.
The ADC is intentionally designed to consume as small as possible current from the supply by combining several circuit techniques such that the ADC features an ultra-low-power (ULP) consumption (<2uW at 1KSPS). The ADC best suits the applications demanding extremely low power consumption like battery-powered products and Internet-of-Things (IoT).
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