LPFPLL is a low-power programmable fractional-N (LPF), phase-locked loop (PLL) for frequency synthesis. It can support a wide range of output frequencies with fine resolution, as well as supporting multiple input reference frequencies.LPFPLL is ideal for use in noisy ASIC/SoC environments due to the excellent supply noise immunity. The lock-detect flag supports real-time monitoring of the phase-locked status. With embedded ESD power clamp circuits and internal initial sequence applied to release from complex configurations and settings,LPFPLL is available as a single macro and can be integrated into any ASIC/SoC easily.
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