USB PHY

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USB PHY



Overview


M SQUARE USB 3.2 PHY IP is designed based on the USB 3.2 Gen2x2 specification from the USB Implementer Forum. It provides bandwidth up to 20Gbps. This high bandwidth benefits consumer/industrial video applications, display and docking applications, cloud computing and automotive applications.


As the leading supplier of USB IP, M SQUARE provides customers with low power, compact area and robust performance IP designed with unique hybrid analog/digital architecture. This IP includes all USB functions (type-C, 20G/10G/5G/480M/12M/1.5Mbps transceiver) and has complete deliverables which ease SOC integration and silicon validation. Our IP is available in a wide variety of process nodes from 40nm to 6/7nm. With compact die size and low pad count, this IP increases the product competitiveness in USB market.



Highlights


Fully compliant USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
Supports 10/12/25/30/19.2/24/27/40MHz crystal oscillator or clock inputs
Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
Integrates an active switch to support the orientation-less connection with USB Type-C connector
Provides an auxiliary CC module IP to support USB Type-C related functions
Supports both wire-bond and flip-chip package type
Provides robust BIST functions for mass production tests
Supports Crystal pad for clock source (Need to use with the XTAL module IP of MSQUARE)
Supports OTG application (Need to use with the IDPAD module IP of MSQUARE)
USB PHY IP is available in 7nm, 12nm, 16nm, 28nm and 40nm process


© 2021 | M SQUARE Ltd. Shanghai | All Rights Reserved | 上海奎芯集成电路设计有限公司


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USB PHY
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m2@m2ipm2.com

marcom@m2ipm2.com

hr@m2ipm2.com

上海市闵行区申长路519号6-2楼6楼

Copyright @ 上海奎芯集成电路设计有限公司  All Rights Reserved  沪ICP备2021035876号  沪公网安备 31011202014381号

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