PCIe PHY

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PCIe PHY



Overview


M SQUARE PCI Express 4.0 PHY IP includes high-speed, highly-efficient and cost-effective transceiver to turbocharge today’s high performance and high bandwidth applications such as data center, automotive, enterprise computing and high-performance embedded system.


The PCIe IP has low power and small silicon footprint as well as robust PHY architecture which tolerates process, voltage and temperature (PVT) variations. The IP integrates high speed mixed signal circuits to support PCIe 4.0 traffic at 16Gbps. It is backward compatible with PCIe 3.1 data rate at 8.0Gbps, PCIe 2.1 data rate at 5.0Gbps and PCIe 1.1 data rate at 2.5Gbps. The multi-tab transceiver design, along with robust BIST and embedded bit error rate (BER) tester and internal eye monitor, enables designers to control, test and monitor signal integrity without expensive test equipment.



Highlights


Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 Specifications
Supports all power saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 spec.
Supports L1 PM/CPM Substates with CLKREQ#
Supports separate REFCLK Independent SSC (SRIS) architecture
Accessible register controls TX PLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength
Supports both FOM and DIR mode for Link-EQ Training
Supports robust BIST/DFT functions for mass production tests
Supports bifurcation with 4-lane x 1 or 2-lane x 2


© 2021 | M SQUARE Ltd. Shanghai | All Rights Reserved | 上海奎芯集成电路设计有限公司


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PCIe PHY
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marcom@m2ipm2.com

hr@m2ipm2.com

上海市闵行区申长路519号6-2楼6楼

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