HBM

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HBM3



Overview


M SQUARE High-Bandwidth Memory generation 3 (HBM3) IP which supports the JESD235E (HBM3) memory standard is designed for high memory throughput and low latency applications. Consisting of PHY and Memory Controller, The M SQUARE HBM3 IP supports HBM3 SDRAM speeds from 4.8Gbps/pin through 6.4Gbps/pin. Flexible configurations as PHY only / PHY + Controller / Controller only are available to meet customer design requirements. The chip area and power consumption are very competitive among similar products.



Highlights


Consists PHY and Memory Controller.
Optional Add-on IPs to achieve best performance.
Optimized for 7nm process.
Supports speed up to 6.4Gbps/pin.
Inclusive of own PLL and IO.
Standard DFI 5.0 support for interoperability.
Flexible configurations available: (PHY only) or ( PHY + Controller) or (Controller only).
Equipped with embedded MCU for flexibility to perform firmware-based training.
PHY IP optionally supports interfacing to itself providing D2D interface solutions.
Minimized area and power consumption.


© 2021 | M SQUARE Ltd. Shanghai | All Rights Reserved | 上海奎芯集成电路设计有限公司


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HBM
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marcom@m2ipm2.com

hr@m2ipm2.com

上海市闵行区申长路519号6-2楼6楼

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