Specialty I/O(LVDS/DDR/eMMC...)
Overview
LPDDR3 I/O is a dynamic memory interface technology with high bandwidth capabilities, which is particularly developed for low-power SOC applications. The LPDDR3 I/O follows interface specification of JEDEC to provide on-die termination (ODT) and support the impedance calibration for ZQ, also it can customize the required functions according to customer specifications. The LPDDR3 I/O solutions are also available at 28nm and 55nm technology process nodes.
Highlights
| Support max. data rate: 1.6Gbps & 1.066Gbps |
| Power-sequence free |
| Provide multi-driving-strength selection |
| Supports low speed data rate of 10Mbps and ultra-low-power mode |
| Provide two receivers (Schmitt trigger and LVCMOS receiver) in a cell, which can be selected by the register. |
| Provide ODT (On-Die Termination) |
| Provide ZQ Calibration |
| Available in 28nm and 55nm process nodes |
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