LPDDR

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LPDDR5X IP



Overview


The M SQUARE LPDDR5X/4X PHY is a transceiver physical layer IP interface solution designed for ASICs and SOCs. Compatible with the universal IP protocol DFI 5.0, it can operate at the data rate up to 8533Mbps with 16-bit data width per channel. With flexible configuration options, the LPDDR5X/4X PHY can be used in a variety of mobile applications supporting LPDDR5X, LPDDR5 and LPDDR4X SDRAMs. With its hybrid analog/digital architecture, M SQUARE’s IP delivers low power consumption, compact area, and robust performance, making it well-suited for LPDDR5X/4X PHY applications.



Highlights


 Compatible with JEDEC standard LPDDR4X , LPDDR5 and LPDDR5X SDRAMs
 Support for data rates up to 8533 Mbps
 DFI5.0 for PHY and Controller interface
 Support PHY independent training mode by Processor
 Support Data Bus Inversion(DBI) mod
 Support 4 trained frequencies
 Support BIST and LOOPBACK mode
 Support background tracking for PVT compensation

Support bypass mode for low-power at low-speed scenario

Compliant with JEDEC standard JESD209-4D and JESD209-5B


© 2022 | M SQUARE Ltd. Shanghai | All Rights Reserved | 上海奎芯集成电路设计有限公司


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