USB PHY

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USB 3.2 PHY



Overview


M SQUARE's USB 3.2 PHY IP is designed based on the USB 3.2 Gen2x1 and USB2.0 specifications from the USB Implementer Forum. It provides bandwidth up to 10Gbps. This high bandwidth benefits consumer/industrial video applications, display and docking applications, cloud computing and automotive applications. 


As the leading supplier of USB IP, M SQUARE provides customers with low power, compact area and robust performance IP designed with unique hybrid analog/digital architecture. This IP includes all USB functions (10G/5G/480M/12M/1.5Mbps transceiver) and has complete deliverables which ease SOC integration and silicon validation. Our IP is available in a wide variety of process nodes from 40nm to 6/7nm. With compact die size and low pad count, this IP increases the product competitiveness in USB market.




Highlights


 Fully compliant USB 3.2 Gen2x1 with PIPE 4.3 and USB2.0 with UTMI+ interface
 Support both host, peripheral and dual role application
 Supports 10/12/25/30/19.2/24/27/40MHz crystal oscillator or clock inputs
 Support TX 3-Tap FFE and RX CTLE+1-Tap DFE for SS+
 Integrates an active switch to support the orientation-less connection with USB Type-C connector
 Provides an auxiliary CC module IP to support USB Type-C related functions
 Provides robust BIST functions for mass production tests
 Supports Crystal pad for clock source (Need to use with the XTAL module IP of M  SQUARE)
 Supports OTG application (Need to use with the IDPAD module IP of M SQUARE)
 USB PHY IP is available in 7nm, 12nm, 16nm, 28nm and 40nm process
Support both wire-bond and flip-chip package type


© 2021 | M SQUARE Ltd. Shanghai | All Rights Reserved | 上海奎芯集成电路设计有限公司


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USB PHY
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