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Join Us


 

Join M SQUARE to make the best IP 

to contribute to the leapfrog of

semiconductor industry!


 

 Intelligence and Outstanding Capablity 

 Entrepreneurial Spirit and Inovation

 Integrity and Teamwork

 

Intelligence and Outstanding Capablity 

 

 

Entrepreneurial Spirit and Inovation

 

 

Integrity and Teamwork

 

Beautiful Office

Openings

Openings

DDR Digital Design Engineer/Lead




The candidate will be mainly responsible for DDR4/5, LPDDR4/5 design.

  • Excellent working attitude and good interpersonal, organizational and communication skills.
  • 5 years or above experience in digital IC design and FPGA emulation flow.
  • Familiar with verilog coding, verification, and IC design flow, including but not limited to RTL design, synthesis, DFT, LEC, STA, CDC, Lint etc.
  • Proficienct in scripting languages like perl, python etc.
  • Familiar with DDR/LPDDR/DFI standards.
  • Experience of DDR/LPDDR PHY/CTRL design.
  • Experienced in SoC architecture and AMBA bus architecture is a plus.
  • Experienced in chip integration is a plus.
  • Experience with system verification is a plus.
  • Experience with analog/digital interface design is a plus.

 

DDR PHY Analog Design Engineer

 

 


 

 

The candidate will be mainly responsible for high-speed receiver and transmitter design.

  • Excellent working attitude and good interpersonal, organizational and communication skills.
  • Proven understanding of analog circuit layout concepts in submicron CMOS technologies.
  • Experience with design and verification tools, including but not limited to Cadence ADE, Voltus-Fi, HSpice, Finesim, XA.
  • Solid knowledge of analog building blocks such as drivers, serializer, receivers, deserializer, phase interpolators, CDR, DLL, LDO, ESD, LUP.
  • Solid knowledge of signal and power integrity on both on-chip and system level
  • Experience on receiver CTLE, DFE design.
  • Experience on clock-based comparator design.
  • Experience on high-speed transmitter design such as pre/de-emphasis, push-pull, and open drain.
  • Experience on conducting PSIJ analysis.
  • Experience on mixed-signal library characterization.
  • A good understanding of IO layouts is required.
  • Familiar with chip floorplanning and packaging design is a plus.

 

DDR PHY Analog Design Lead

 

 


 

 

The candidate will be mainly responsible for analog phy top architecture and integration including phy planning, timing budgeting, and physical design.

  • Excellent working attitude and good interpersonal, organizational and communication skills.
  • Proven understanding of analog circuit layout concepts in submicron CMOS technologies.
  • Experience with design and verification tools, including but not limited to Cadence ADE, Voltus-Fi, HSpice, Finesim, XA.
  • Good knowledge of analog building blocks such as drivers, receivers, phase interpolators, CDR, DLL, LDO, ESD, LUP.
  • Understand the trade off between analog and digital building blocks.
  • Ability to collaborate with digital and software to optimize phy architecture.
  • Solid knowledge of full custom logic design and on-chip signal and power integrity effects.
  • Experience on high-speed system timing/jitter budgeting.
  • Experience on analog phy integration such as library characterization, STA, EM, IR .
  • Experience on power, performance, area optimization.
  • Experience on testing such as DFT, BIST is a plus.
  • Familiar with chip floorplanning and packaging design is a plus.
  • Proficienct in scripting languages like perl, python, etc., is a plus.

MIPI Analog Design Engineer




The candidate will be mainly responsible for MIPI C/D/M-PHY design.

  • Excellent working attitude and good interpersonal, organizational and communication skills.
  • Proven understanding of analog circuit layout concepts in submicron CMOS technologies
  • Experience with design and verification tools, including but not limited to Cadence ADE, Voltus-Fi, HSpice, Finesim, XA.
  • Solid knowledge of analog building blocks such as drivers, serializer, receivers, deserializer, phase interpolators, CDR, DLL, LDO, ESD, LUP.
  • Experience on receiver MIPI PMA design is a plus.
  • Experience on receiver MIPI CPHY CDR is a plus.
  • Solid knowledge of signal and power integrity on both on-chip and system level is a plus

MIPI Digital Design Engineer




The candidate will be mainly responsible for MIPI DSI/CSI and PCS of C/D/M-PHY design.

  • Excellent working attitude and good interpersonal, organizational and communication skills.
  • 4 years or above experience in digital IC design and FPGA emulation flow.
  • Familiar with verilog coding, verification, and IC design flow, including but not limited to RTL design, synthesis, DFT, LEC, STA, CDC, Lint etc.
  • Proficienct in scripting languages like perl, python etc.
  • Experience of MIPI digital PHY/controller or other analog-digital co-development is a plus.
  • Experienced in SoC architecture and AMBA bus architecture is a plus.
  • Experienced in chip integration is a plus.
  • Experience with system verification is a plus.
  • Experience with low power improvement is a plus.
  • Experience with analog/digital interface design is a plus.

High Speed SERDES Analog Design Engineer




The candidate will be mainly responsible for PCIe/USB analog PHY design.

  • Excellent working attitude and good interpersonal, organizational and communication skills.
  • Proven understanding of analog circuit layout concepts in submicron CMOS technologies.
  • Experience with design and verification tools, including but not limited to Cadence ADE, Voltus-Fi, HSpice, Finesim, XA.
  • Solid knowledge of analog building blocks such as drivers, serializer, receivers, deserializer, phase interpolators, CDR, DLL, LDO, ESD, LUP.
  • Experience on PCIe/USB PMA design is a strong plus.
  • Experience on receiver CTLE, DFE design is a plus.
  • Experience on system level modeling is a strong plus.
  • Solid knowledge of signal and power integrity on both on-chip and system level is a plus.

High Speed SERDES Digital Design Engineer




The candidate will be mainly responsible for PCIe/USB digital PHY/CTRL design.

  • Excellent working attitude and good interpersonal, organizational and communication skills.
  • 6 years or above experience in digital IC design and FPGA emulation.
  • Familiar with verilog coding, verification, and IC design flow, including but not limited to RTL design, synthesis, DFT, LEC, STA, CDC, Lint etc.
  • Proficienct in scripting languages like perl, python etc.
  • Experience of PCIe/USB digital PHY/controller is a plus.
  • Experienced in SoC architecture and AMBA bus architecture is a plus.
  • Experienced in chip integration is a plus.
  • Experience with system verification is a plus.
  • Experience with low power improvement is a plus
  • Experience with analog/digital interface design is a plus.


JOIN US 

Please submit your resume to: hr@m2ipm2.com

Mail Subject: name + position applied + preferred location

 

 

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m2@m2ipm2.com

marcom@m2ipm2.com

hr@m2ipm2.com

6th Floor, Building 6-2, No. 519 Shenchang Rd, Minhang, Shanghai, 201107

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m2@m2ipm2.com

marcom@m2ipm2.com

hr@m2ipm2.com

6th Floor, Building 6-2, No. 519 Shenchang Rd,

Minhang, Shanghai, 201107

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